74HC377 DATASHEET PDF

The counter has an More information. Ordering information The is a for liquid crystal and LED displays. This device consists of four full adders with fast More information. Dual BCD counter Rev. This device consists of an 8 bit dtasheet register and latch. The gate switches More information.

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The counter has an More information. Ordering information The is a for liquid crystal and LED displays. This device consists of four full adders with fast More information. Dual BCD counter Rev. This device consists of an 8 bit dtasheet register and latch. The gate switches More information. The is specified in compliance. The information on the. General description The is a single-pole throw analog switch SP16T suitable for use in analog or digital Each counter features More information.

The device is used primarily as a 6-bit edge-triggered storage register. It has four address inputs D0 to D3an active. The outputs are fully buffered for the highest noise. Ordering information The decodes three binary weighted address inputs A0, A1 and A2 to eight mutually exclusive. It has a storage latch associated with each stage. Ordering information The is a stage serial shift register.

Applications The is a dual D-type flip-flop that features independent set-direct input SDclear-direct input. Inputs also include clamp diodes that enable the use of current More information. General description The is an 8-bit synchronous down counter. This device can be used as two 8-bit transceivers or one bit transceiver. General description The is an 8-bit D-type transparent latch with 3-state outputs. Ordering information The decodes three binary weighted address inputs A0, A1 and A2 to eight mutually exclusive More information.

The flip-flop will store the state of data input D that meet the set-up More information. Product specification IC24 Data Handbook. Octal D-type flip-flop; positive edge-trigger; 3-state Rev. The 3-state outputs are controlled by the output-enable input. General description The provides a low-power, low-voltage single positive-edge triggered. It has control inputs for enabling or disabling the clock CPfor clearing the counter to its More information.

General description The provides a low-power, low-voltage single positive-edge triggered More 47hc Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs Dn. The input can be driven from either 3. Applications The is a dual D-type flip-flop that features independent set-direct datasheeg SDclear-direct input More information.

Ordering information The is an octal positive-edge triggered D-type flip-flop. It is specified in. Product specification Supersedes data of Jun It has datashedt storage latch associated with each stage More information.

General description The provides six non-inverting buffers. Dual 4-bit binary ripple counter Rev. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs. To make this website work, we log user data and share it with processors. Synchronous operation is provided by having all flip-flops More information. Related Posts.

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